search > New York jobs > New York computer/technical

Posted: Saturday, October 12, 2013 11:02 AM

Semiconductor jobs in NY State SRAM, Photolithography, TCAD, Memory Device, Technology & Integration, Yield Defect

We will consider anyone with a reasonable combination of experience in the following and will tailor a job around you
Our organization makes us flexible to work with you and your career in the semiconductor industry

You must have industry experience
In some cases travel to and working in Europe may be required depending on your skills and availability to work in the EU

In all cases, We always have several other semiconductor jobs not yet published on the WWW, listed on or posted to our company website

A New Beginning-Genesis 2

Prior to calling you may want to review the following linkedin profile(s)-job lists; you may need to be “logged out” of your linkedin profile to do so. You may also want to connect with me via 1 or more profiles to receive my updates. Would you please email me any job titles and locations from the list you want to discuss prior to calling me? We will discuss the position you selected as well and cover all our bases

Semiconductor current and most up to date jobs are listed on-

The ideal candidate has worked for these companies:
Samsung, Intel, AMD, Texas Instruments, Micron, ST Micro and other semiconductor companies

Benefits - Full
Relocation Assistance Available - Yes
Bonus Eligible - Yes
Interview Travel Reimbursed - Yes

SRAM Device Technologist
We need an SRAM device engineer and not interested in SRAM design or IC, ASIC, compilers. They will have device engineering, SRAM bit cell development integration and characterization experience.
Static random-access memory SRAM Cell, possibly layout, curvature
SRAM Device engineer will be responsible for working on high density SRAM memory in state-of-the-art CMOS logic process technologies including 20nm high-k/MG and beyond. In this position, you will both develop and integrate high density SRAM devices into the current Logic process flows, optimized for performance, reliability, device mismatch, yield and ease of manufacturing.
You will be responsible for all aspects of the SRAM module development. This includes the structural development of SRAM bit cells, SRAM device development, integration into baseline processes, characterization of the cells, and analysis of parametric data bridging into yield engineering activity.
This position involves activities associated with the development and transfer to manufacturing of both high-performance and low-power CMOS technologies. Basic device concepts are received from Research and are tested and integrated into full technology solutions to satisfy the needs of our foundry customers, working closely with internal manufacturing facilities.
The role requires interaction with
-Device modeling group and process-integration groups to determine adequate electrical and layout design rules. Based on technology definition to meet customer requirements, with the help of the modeling group, you will define electrical & process parametric targets for SRAM device spice models.
-Test and Characterization group to analyze and debug device related issues during process development. Your work will involve the use of JMP, and other software that enables statistical analysis of large parametric and reliability data sets.
-Layout and parametric groups to design and layout test structures (macros), working on setting up parametric programs. You will interface with process engineers (or Integration Engineers) to define and analyze appropriate process/device DOE (Design of Experiment). You will also routinely work directly with engineers in process Integration, starting with reliability issues ultimately leading to new process qualifications and improved reliability.
Successful candidates for this position will have: A minimum of 5-7 years of experience in semiconductor device engineering after Master and/or Ph.D study and SRAM process integration knowledge and device module development experience, or related experience with a similar skill set. A thorough knowledge of SRAM functional operation, CMOS device physics, state-of-the-art CMOS logic process technologies, and logic process integration is preferred. Ability to aggressively execute complex process/device experiments and focus on solving problems individually or as part of a team is desirable. Experience with scribe test structure layout( testing macros), parametric program setup, and bench measurements and familiarity of electrical characterization is a plus.
Specific Responsibilities:- Successful candidates will design, execute, and analyze experiments aimed at the creation and optimization of leading-edge silicon transistor technology (20nm technology generation and beyond) within a development environment. This will include both physical and electrical data analysis, as well as extensive coordination with the joint technology development alliance integration, device, and unit process module groups.
-SRAM cell device design and performance optimization across different cells
-Mismatch(Avt) improvement plan and execution to meet technology Vmin requirement for low leakage and performance SRAM cell families at a given technology
-Seamless interface role between unit process module, integration and logic device team in terms of SRAM device maturity learning during technology development
-Standby leakage management skills by specific device leakage control engineering by taking all aspects with trade-offs into account
-Silicon HW learning planning and execution as well as electrical data analysis
-SRAM device targeting to meet technology requirement and working closely with modeling groups to ensure high quality spice model development
- In addition to the achievement industry-leading device characteristics, variability (mismatch) and reliability must be monitored and controlled to ensure manufacturability.
- Interaction with customer design groups will also be a facet of this position in order to define technology requirements and parametric goals for our technology roadmaps.
- Strong fundamental understanding of solid state device physics, sub-0.1-micron FET architectures, and the implications of device characteristics and performance on technology and product behavior.
- Fundamental understanding of unit process and module interactions (including all FEoL unit processes, such as shallow trench formation, fill and CMP, gate dielectric and electrode formation, implant and implant masking and activation, and gate spacer and silicide contact formation) on electrical parametric, product yield, and performance behavior.
- In addition to technical proficiency, all candidates must have proven project management skills, peer leadership skills, and be able to mentor more junior engineers.
- Direct experience in low-leakage / low-power device design and optimization is strongly desired, and additional technical experience in FEOL reliability, defect inspection and reduction, yield analysis, and/or test structure design is a plus.

OPC Photolithography Engineer exp
have OPC (optical proximity characterization) and photolithography experience.
develop and qualify OPC technology on 22nm node and beyond. He or She will also transfer and enable OPC solutions in OUR manufacturing. Candidate should possess strong lithography/OPC knowledge, in FEOL and/or BEOL; and good understanding of high performance CMOS patterning/design integration. Candidate should be experienced on lithography/OPC process development and must be capable of collaborating with upstream and downstream development teams. Previous technology development and transfer experience is a plus.
develop OPC technology for 22nm and beyond generations. Candidates should have working knowledge of Lithography, OPC (both modeling and correction), mask data prep, and design rules.
• Candidate for this position must be self-motivated and is capable of driving development projects with minimum supervision. Candidate will be required to work well within an alliance team for technology development, and also within a OUR internal team for technology transfer and enablement.
•Lithography and/or OPC experience preferred.
•Working knowledge of industrial grade OPC/Lithography software.
- Fundamental understanding of lithography and OPC processes, and lithography/OPC integration is required, and additional technical experience in lithography flow, OPC flow, and mask flow is a plus.

Manager TCAD
manage and organize Technology Computer Aided Design TCAD support for the development of new technology nodes (20nm, 14mm and below) using TCAD software (Taurus & Sentaurus platforms).
work closely with the device management team and the PI management teams.
work independently to solve the TCAD issues and to work as TCAD expert in larger team providing support to solve critical device and process integration issues.
- technical leadership position for :
Calibration of the TCAD process&device decks
Transistor performance optimization
Advanced process simulations for new process architectures comparison
Advanced device simulations for CMOS and NVM devices - 3D simualtions for Sram and SER modeling
Calibration of the TCAD process&device decks
Transistor performance optimization
Advanced process simulations for new process archs
Advanced device simulations for CMOS & NVM device

Memory Device Research Engineer- Europe for first 2 years then NY ST
focus on advanced memory device research
Development of processes and process flows for advanced resistive memory devices.
Electrical and structural characterization of memory structures and devices and analysis of the data.
Technology transfer to our companies internal clients.
Fundamental understanding of memory device operation and physics.
Knowledge of device characterization methods - structural and electrical.
Knowledge of semiconductor processing (deposition, thermal, etc) chemistry and physics.
Familiarity with material and device modeling tools and methods.
Hands-on experience with advanced memory device research
Familiarity with material and device modeling tools and methods.
Hands-on experience with advanced memory device research

Technology & Integration Engineer - EFUSE
Develop, qualify the new Electronic Fuses efuse technology and transfer for volume production ramp up
Interface with device and process integration team for technology development
Work with characterization and reliability team for failure analysis and qualification
Data analysis for efuse characterization and qualification
Efuse p-cell generation for fuse design evaluation
Work with design/enablement team for efuse kit development
Maintain physical and electrical specification of efuse in design manual
Report and document the technical issues and drive the solutions
Join in the critical technical decisions with team members
Understanding in BEOL reliability (Electro migration) and its failure mechanism
Experience in efuse technology development and qualification
Strong data analysis skills which can handle large amount of data and can extract meaningful data from them

Yield Defect Engineer
exp as CFM Defect Engineer. Worked as a Defect Yield Engineer, bright/dark field experience and worked on KLA and/or AMAT Systems listed, KLA2835
SEMVISION G4, G5 Defect engineers
provide accurate defect related analysis relating to efforts to implement advanced technology nodes
Optimization of throughput and tool utilization for manufacturability in preparation for the eventual transfer to mass production in 300mm facilities is the final goal.
Formulate effective inline inspection strategy & methodology to support advanced technology development activities.
Drive continuous improvement to streamline CFM workflow on inline defect detection efficiency and defect monitoring.
Establish DOIs defect characterization techniques and drive inline CFM recipes optimization and innovation to meet defect capture rate and nuisance rate requirements.
Drive equipment vendors to improve or optimized applications for development requirements
Define and maintain relevant defect matrixes for product performance, reliability, yield, and breakeven utilization targets for cost optimization.
Design, execute and analyze partition studies to evaluate process results or equipment baseline performances with a view to achieve industry competitive standards.
Serve as a technical leader for defect metrology for collaboration with other 300mm facilities or within the alliances and support tool selection strategies in emerging facilities for inspection equipment and software solutions
Provide effective leadership and mentorship for defect technicians executing defect scans or data reviews in support of the program.
Required hands-on for day to day review of information, evaluation of defect monitoring strategies and understanding of defect mechanisms with the mindset of making a difference.
Required to work in a clean-room environment to supervise, execute or oversee activities.
Experience with bright field and dark field inspection tools including tool maintenance and recipe development. Familiarize with KT defect scan and HMI e-beam scan tools are strongly desired
Working experience in CMOS process and process module/equipment (200mm/300mm) are strongly desired
Experience working with vendor in equipment procurement is highly desired
Working knowledge in SPC or DOE methodology is preferred
Prior employment in a vendor specializing in defect tool applications would have a strong advantage
Knowledge of JMP/Klarity Defect software platforms
defect and yield engineering
using KLA, AMAT tools.

Please feel free to call 860 889 4141, until 9 PM Eastern, 7 days a week
Regards, ciao, Namaste, Peace,
Joseph Anthony Vaccariello

• Location: Bronx, Brooklyn, Fairfield, Long Island, Manhattan, NY State, Queens, Staten Island, Westchester

• Post ID: 38563365 newyork is an interactive computer service that enables access by multiple users and should not be treated as the publisher or speaker of any information provided by another information content provider. © 2015